CY7C1394BV18 - 1.8V Synchronous Pipelined SRAM

This page provides the datasheet information for the CY7C1394BV18, a member of the CY7C1392BV18 1.8V Synchronous Pipelined SRAM family.

Product Overview

Cypress Semiconductor

Part number	CY7C1394BV18
Manufacturer	Cypress Semiconductor
File Size	386.82 KB
Description	1.8V Synchronous Pipelined SRAM
Datasheet	CY7C1394BV18 Datasheet
Additional preview pages of the CY7C1394BV18 datasheet.

18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36).
300 MHz clock for high bandwidth.
2-word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simplify data capture in high-speed systems.

CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C131E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C136AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C136E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)
CY7C1371S - 18-Mbit (512K x 36) Flow-Through SRAM (Cypress)
CY7C1372C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)

Other Datasheets by Cypress Semiconductor

Published: Nov 6, 2016 |