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CY7C1393KV18 - 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture

Download the CY7C1393KV18 datasheet PDF. This datasheet also covers the CY7C1392KV18 variant, as both devices belong to the same 18-mbit ddr ii sio sram two-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • 18-Mbit density (2M × 8, 1M × 18).
  • 333-MHz clock for high bandwidth.
  • Two-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
  • Synchronous int.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1392KV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Cypress

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1393BV18 1.8V Synchronous Pipelined SRAM
CY7C139 4K x 8/9 Dual-Port Static RAM
CY7C1392BV18 1.8V Synchronous Pipelined SRAM
CY7C1392KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
CY7C1394BV18 1.8V Synchronous Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features ■ 18-Mbit density (2M × 8, 1M × 18) ■ 333-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Synchronous internally self timed writes ■ DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH ■ Operates similar to DDR I device with one cycle read latency when DOFF is asserted LOW ■ 1.