CY7C1393KV18 Datasheet PDF - Cypress Semiconductor 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Specs

CY7C1393KV18 - 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture

This page provides the datasheet information for the CY7C1393KV18, a member of the CY7C1392KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture family.

Datasheet Summary

Features

18-Mbit density (2M × 8, 1M × 18).
333-MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
Synchronous int.

Datasheet Details

Part number	CY7C1393KV18
Manufacturer	Cypress Semiconductor
File Size	587.97 KB
Description	18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
Datasheet	CY7C1393KV18 Datasheet
Additional preview pages of the CY7C1393KV18 datasheet.

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Full PDF Text Transcription

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CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features ■ 18-Mbit density (2M × 8, 1M × 18) ■ 333-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Synchronous internally self timed writes ■ DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH ■ Operates similar to DDR I device with one cycle read latency when DOFF is asserted LOW ■ 1.

Published: Mar 13, 2017 |