CY7C1393KV18 - 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture

This page provides the datasheet information for the CY7C1393KV18, a member of the CY7C1392KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture family.

Product Overview

Cypress Semiconductor

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Datasheet Details

Part number	CY7C1393KV18
Manufacturer	Cypress Semiconductor
File Size	587.97 KB
Description	18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
Datasheet	CY7C1393KV18 Datasheet
Additional preview pages of the CY7C1393KV18 datasheet.

CY7C1393KV18 Product details

Features

18-Mbit density (2M × 8, 1M × 18).
333-MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
Synchronous int.

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Published: Mar 13, 2017 |