CY7C1393KV18
CY7C1393KV18 is 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture manufactured by Cypress.
Features
- 18-Mbit density (2M × 8, 1M × 18)
- 333-MHz clock for high bandwidth
- Two-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- Synchronous internally self timed writes
- DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH
- Operates similar to DDR I device with one cycle read latency when DOFF is asserted LOW
- 1.8 V core power supply with HSTL inputs and outputs
- Variable drive HSTL output buffers
- Expanded HSTL output voltage (1.4 V- VDD)
- Supports both 1.5 V and 1.8 V I/O...
