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CY7C1444AV33 - 36-Mbit Pipelined DCD Sync SRAM

Description

The CY7C1444AV33 SRAM integrates 1M × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for

Features

  • Supports bus operation up to 250 MHz.
  • Available speed grades are 250 MHz and 167 MHz.
  • Registered inputs and outputs for pipelined operation.
  • Optimal for performance (double-cycle deselect).
  • Depth expansion without wait state.
  • 3.3 V core power supply.
  • 2.5 V/3.3 V I/O power supply.
  • Fast clock-to-output times.
  • 2.6 ns (for 250-MHz device).
  • Provide high-performance 3-1-1-1 access rate.
  • User-selectable burst counter supporting Intel Pentium int.

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Full PDF Text Transcription

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CY7C1444AV33 36-Mbit (1M × 36) Pipelined DCD Sync SRAM 36-Mbit (1M × 36) Pipelined DCD Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250 MHz and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ■ Depth expansion without wait state ■ 3.3 V core power supply ■ 2.5 V/3.3 V I/O power supply ■ Fast clock-to-output times ❐ 2.
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