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CY7C1445KV33 - 36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM

This page provides the datasheet information for the CY7C1445KV33, a member of the CY7C1444KV33 36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM family.

Description

The CY7C1444KV33/CY7C1445KV33 SRAMs integrate 1M × 36/2M × 18 SRAM cells with advanced sy

Features

  • Supports bus operation up to 250 MHz.
  • Available speed grades is 250 MHz.
  • Registered inputs and outputs for pipelined operation.
  • Optimal for performance (double-cycle deselect).
  • Depth expansion without wait state.
  • 3.3-V core power supply.
  • 2.5-V or 3.3-V I/O power supply.
  • Fast clock-to-output times.
  • 2.5 ns (for 250-MHz device).
  • Provide high-performance 3-1-1-1 access rate.
  • User-selectable burst counter supporting interleaved or line.

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Datasheet preview – CY7C1445KV33

Datasheet Details

Part number CY7C1445KV33
Manufacturer Cypress Semiconductor
File Size 847.38 KB
Description 36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM
Datasheet download datasheet CY7C1445KV33 Datasheet
Additional preview pages of the CY7C1445KV33 datasheet.

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Full PDF Text Transcription

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CY7C1444KV33 CY7C1445KV33 36-Mbit (1M × 36/2M × 18) Pipelined DCD Sync SRAM 36-Mbit (1M × 36/2M × 18) Pipelined DCD Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades is 250 MHz ■ Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ■ Depth expansion without wait state ■ 3.3-V core power supply ■ 2.5-V or 3.3-V I/O power supply ■ Fast clock-to-output times ❐ 2.
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