900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Cypress Semiconductor Electronic Components Datasheet

CY7C1460KVE25 Datasheet

36-Mbit (1M x 36/2M x 18) Pipelined SRAM

No Preview Available !

CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
36-Mbit (1M × 36/2M × 18) Pipelined SRAM
with NoBL™ Architecture (With ECC)
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
Features
Pin-compatible and functionally equivalent to ZBT™
Supports 250-MHz bus operations with zero wait states
Available speed grades are 250 MHz, 200 MHz, and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte Write capability
2.5-V core power supply
2.5-V I/O power supply
Fast clock-to-output times
2.5 ns (for 250-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
CY7C1460KV25, CY7C1462KV25, CY7C1460KVE25 and
CY7C1462KVE25 available in JEDEC-standard Pb-free
100-pin TQFP, and Pb-free and non Pb-free 165-ball FBGA
packages.
IEEE 1149.1 JTAG-Compatible Boundary Scan
Burst capability — linear or interleaved burst order
“ZZ” sleep mode option
On-chip error correction code (ECC) to reduce soft error rate
(SER)
Selection Guide
Maximum access time
Maximum operating current
Description
Functional Description
The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/
CY7C1462KVE25 are 2.5 V, 1M × 36/2M × 18 synchronous
pipelined burst SRAMs with No Bus Latency™ (NoBL logic,
respectively. They are designed to support unlimited true
back-to-back read/write operations with no wait states. The
CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/
CY7C1462KVE25 are equipped with the advanced NoBL logic
required to enable consecutive read/write operations with data
being transferred on every clock cycle. This feature dramatically
improves the throughput of data in systems that require frequent
write/read transitions. The CY7C1460KV25/CY7C1462KV25/
CY7C1460KVE25/CY7C1462KVE25 are pin-compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the byte write selects
BWa–BWd for CY7C1460KV25/CY7C1460KVE25 and
BWa–BWb for CY7C1462KV25/CY7C1462KVE25 and a write
enable (WE) input. All writes are conducted with on-chip
synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
250 MHz 200 MHz 167 MHz Unit
2.5 3.2 3.4 ns
× 18 220 190 170 mA
× 36 240 210 190
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-66679 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 5, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1460KVE25 Datasheet

36-Mbit (1M x 36/2M x 18) Pipelined SRAM

No Preview Available !

CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Logic Block Diagram – CY7C1460KV25
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
BWc
BWd
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPa
DQPb
DQPc
DQPd
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Logic Block Diagram – CY7C1462KV25
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
N
G
E
DQs
DQPa
DQPb
INPUT
REGISTER 1 E
INPUT
REGISTER0 E
OE
CE1
CE2
CE3
ZZ
Document Number: 001-66679 Rev. *I
READ LOGIC
Sleep
Control
Page 2 of 32


Part Number CY7C1460KVE25
Description 36-Mbit (1M x 36/2M x 18) Pipelined SRAM
Maker Cypress Semiconductor
Total Page 30 Pages
PDF Download

CY7C1460KVE25 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 CY7C1460KVE25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM
Cypress Semiconductor





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy