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CY7C1463KV33 - 36-Mbit (1M x 36/2M x 18) Flow-Through SRAM

Download the CY7C1463KV33 datasheet PDF (CY7C1461KV33 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 36-mbit (1m x 36/2m x 18) flow-through sram.

Features

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
  • Supports up to 133 MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin compatible and functionally equivalent to ZBT™ devices.
  • Internally self timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow through operation.
  • Byte write capability.
  • 3.3 V and 2.5 V I/O power supply.
  • Fast clock-to-outpu.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1461KV33-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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CY7C1461KV33 CY7C1463KV33 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture Features ■ No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states ❐ Data is transferred on every clock ■ Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V and 2.5 V I/O power supply ■ Fast clock-to-output times ❐ 6.
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