CY7C1515AV18
Features
- Configurations
CY7C1511AV18
- 8M x 8 CY7C1526AV18
- 8M x 9 CY7C1513AV18
- 4M x 18 CY7C1515AV18
- 2M x 36
Separate independent read and write data ports
- Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches Echo clocks (CQ and CQ) simplify data capture in high-speed systems Single multiplexed address input bus latches address inputs for read and write ports Separate port selects for depth expansion Synchronous internally self-timed writes QDR-II operates with 1.5 cycle read latency when the Delay Lock Loop (DLL) is enabled Operates as a QDR-I device with 1 cycle read latency in DLL off mode Available in x 8, x 9, x 18, and x 36...
