CY7C1522KV18 Datasheet

Manufacturer: Cypress (now Infineon)

Datasheet Details

Part number	CY7C1522KV18
Datasheet	CY7C1522KV18_CypressSemiconductor.pdf
File Size	906.43 KB
Manufacturer	Cypress (now Infineon)
Description	72-Mbit DDR II SIO SRAM 2-Word Burst Architecture

CY7C1522KV18 Overview

The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations.

CY7C1522KV18 Key Features

SRAM uses rising edges only Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches
Supports both 1.5 V and 1.8 V IO supply Available in 165-ball FBGA Package (13 × 15 × 1.4 mm) Offered in both Pb-free an

More Datasheets from Cypress (now Infineon)

See all Cypress (now Infineon) datasheets

Part Number	Description
CY7C1522AV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522JV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522V18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1520KV18	72-Mbit DDR-II SRAM Two-Word Burst Architecture
CY7C1520V18	1.8V Synchronous Pipelined SRAM
CY7C1521KV18	72-Mbit DDR II SRAM Four-Word Burst Architecture
CY7C1521V18	1.8V Synchronous Pipelined SRAM
CY7C1523AV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1523JV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1523KV18	72-Mbit DDR II SIO SRAM 2-Word Burst Architecture

Datasheet Details

CY7C1522KV18 Overview

CY7C1522KV18 Key Features

More Datasheets from Cypress (now Infineon)

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