CY7C1613KV18 - 144-Mbit QDR II SRAM Four-Word Burst Architecture

Cypress Semiconductor

Datasheet Details

Separate independent read and write data ports.
Supports concurrent transactions.
333 MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo cl.

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