CY7C1620KV18 Datasheet 144-mbit Ddr Ii Sram Two-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1618KV18/CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture 144-Mbit DDR II SRAM Two-Word Burst.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

Part number	CY7C1620KV18
Manufacturer	Cypress (now Infineon)
File Size	569.14 KB
Description	144-Mbit DDR II SRAM Two-Word Burst Architecture
Datasheet	CY7C1620KV18 CY7C1618KV18 Datasheet (PDF)

144-Mbit density (8M × 18, 4M × 36).
333 MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
Synchronous i.

Part Number	Description
CY7C1625KV18	144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1612KV18	144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1613KV18	144-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1614KV18	144-Mbit QDR II SRAM Two-Word Burst Architecture
CY7C1615KV18	144-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1618KV18	144-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C164	16K x 4 Static RAM
CY7C1643KV18	144-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1645KV18	144-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1648KV18	144-Mbit DDR II+ SRAM Two-Word Burst Architecture