CY7C1625KV18 Description
CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 144-Mbit QDR® II SRAM Two-Word Burst Architecture 144-Mbit QDR® II SRAM Two-Word Burst.
CY7C1625KV18 Key Features
- Separate independent read and write data ports
- Supports concurrent transactions
- 360-MHz clock for high bandwidth
- Two-word burst on all accesses
- Double data rate (DDR) interfaces on both read and write ports
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock
- Echo clocks (CQ and CQ) simplify data capture in high-speed
- Single multiplexed address input bus latches address inputs