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CY7C1625KV18 - 144-Mbit QDR II SRAM Two-Word Burst Architecture

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 360-MHz clock for high bandwidth.
  • Two-word burst on all accesses.
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 720 MHz) at 360 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) sim.

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Part Number Description
CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1612KV18 144-Mbit QDR II SRAM Two-Word Burst Architecture
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CY7C1614KV18 144-Mbit QDR II SRAM Two-Word Burst Architecture
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 144-Mbit QDR® II SRAM Two-Word Burst Architecture 144-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 360-MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 720 MHz) at 360 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Single multiplexed address input bus latches address inputs for both read and write ports ■ Separate port selects for depth expansion ■ Synchron