* 18-Mbit density (1M × 18, 512K × 36)
* 550-MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
* Available in 2.5 clock cycle latency
* Two input clocks (K and K) for
CY7C2168KV18 Datasheet (624.09 KB)
CY7C2168KV18
Cypress Semiconductor
624.09 KB
18-mbit ddr ii+ sram two-word burst architecture.
CY7C2168KV18/CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 18-Mbit DDR II+ SRAM Two-Word Burst Arch.
📁 Related Datasheet
CY7C2163KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C2245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C225 512 x 8 Registered PROM (Cypress)
CY7C225A 512 x 8 Registered PROM (Cypress Semiconductor)
CY7C2262XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C2263KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2263XV18 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C2264XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (Cypress Semiconductor)
TAGS
Image Gallery
