CY7C2644KV18 Datasheet | Cypress

CY7C2642KV18/CY7C2644KV18 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features - Separate independent read and write data ports - Supports concurrent transactions - 333-MHz clock for high bandwidth - Two-word burst for reducing address bus frequency - Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz - Available in 2.0-clock cycle latency - Two input clocks (K and K) for precise DDR timing - SRAM uses rising edges only - Echo clocks (CQ and CQ) simplify data capture in high-speed systems - Data valid pin (QVLD) to indicate valid data on the output - On-die termination (ODT) feature - Supported for D[x:0], BWS[x:0], and K/K inputs - Single multiplexed address input bus latches address inputs for both read and write ports - Separate port selects for depth expansion -...