Datasheet4U Logo Datasheet4U.com

CY7C265 - 8K x 8 Registered PROM

Datasheet Summary

Description

The CY7C265 is a 8192 x 8 registered PROM.

It is organized as 8,192 words by 8 bits wide, and has a pipeline output register.

Features

  • CMOS for optimum speed/power.
  • High speed (Commercial).
  • 15 ns address set-up.
  • 12 ns clock to output.
  • Low power.
  • 660 mW (Commercial).
  • On-chip edge-triggered registers.
  • Ideal for pipelined microprogrammed systems.
  • EPROM technology.
  • 100% programmable.
  • Reprogrammable (CY7C265W).
  • 5V ±10% VCC, commercial and military.
  • Capable of withstanding >2001V static discharge.
  • Slim 28-pin.

📥 Download Datasheet

Datasheet preview – CY7C265

Datasheet Details

Part number CY7C265
Manufacturer Cypress Semiconductor
File Size 327.46 KB
Description 8K x 8 Registered PROM
Datasheet download datasheet CY7C265 Datasheet
Additional preview pages of the CY7C265 datasheet.

📁 Similar Datasheet

  • CY7C225 - 512 x 8 Registered PROM (Cypress)
  • CY7C277 - 32K x 8 Reprogrammable Registered PROM (Cypress)
  • CY7C008 - 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
  • CY7C008V - 3.3V 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
  • CY7C009 - 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
  • CY7C009V - 128K x 8 Dual-Port Static RAM (Cypress)
  • CY7C018 - 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
  • CY7C018V - 3.3V 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
  • CY7C019 - 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
  • CY7C019V - 3.3V 64K/128K x 8/9 Dual-Port Static RAM (Cypress)
Other Datasheets by Cypress Semiconductor
  • CY7C261 - 8K x 8 Power-Switched and Reprogrammable PROM
  • CY7C263 - 8K x 8 Power-Switched and Reprogrammable PROM
  • CY7C264 - 8K x 8 Power-Switched and Reprogrammable PROM
  • CY7C2642KV18 - 144-Mbit QDR II+ SRAM Two-Word Burst Architecture
  • CY7C2644KV18 - 144-Mbit QDR II+ SRAM Two-Word Burst Architecture
  • CY7C266 - 8Kx8 Power-Switched and Reprogrammable PROM
  • CY7C2663KV18 - 144-Mbit QDR II+ SRAM Four-Word Burst Architecture
  • CY7C2665KV18 - 144-Mbit QDR II+ SRAM Four-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
65 CY7C265 8K x 8 Registered PROM Features • CMOS for optimum speed/power • High speed (Commercial) — 15 ns address set-up — 12 ns clock to output • Low power — 660 mW (Commercial) • On-chip edge-triggered registers — Ideal for pipelined microprogrammed systems • EPROM technology — 100% programmable — Reprogrammable (CY7C265W) • 5V ±10% VCC, commercial and military • Capable of withstanding >2001V static discharge • Slim 28-pin, 300-mil plastic or hermetic DIP If the asynchronous enable (E) is being used, the outputs may be disabled at any time by switching the enable to a logic HIGH, and may be returned to the active state by switching the enable to a logic LOW.
Published: |