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CY7C2644KV18 Datasheet 144-mbit Qdr Ii+ Sram Two-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C2642KV18/CY7C2644KV18 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 333-MHz clock for high bandwidth.
  • Two-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
  • Available in 2.0-clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed sys.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C264 8K x 8 Power-Switched and Reprogrammable PROM
CY7C2642KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture
CY7C261 8K x 8 Power-Switched and Reprogrammable PROM
CY7C263 8K x 8 Power-Switched and Reprogrammable PROM
CY7C265 8K x 8 Registered PROM
CY7C266 8Kx8 Power-Switched and Reprogrammable PROM
CY7C2663KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C2670KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C2163KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture

CY7C2644KV18 Distributor