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CYF1072V - 18/36/72-Mbit Programmable 2-Queue FIFOs

This page provides the datasheet information for the CYF1072V, a member of the CYF1018V 18/36/72-Mbit Programmable 2-Queue FIFOs family.

Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device.

It has independent read and write ports, which can be clocked up to 100 MHz.

User can configure input and output bus sizes.

Features

  • Functional.

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Datasheet Details

Part number CYF1072V
Manufacturer Cypress (now Infineon)
File Size 911.18 KB
Description 18/36/72-Mbit Programmable 2-Queue FIFOs
Datasheet download datasheet CYF1072V Datasheet
Additional preview pages of the CYF1072V datasheet.

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Full PDF Text Transcription

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CYF1018V, CYF1036V CYF1072V 18/36/72-Mbit Programmable 2-Queue FIFOs 18/36/72-Mbit Programmable 2-Queue FIFOs Features ■ Functional Description The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 100 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 3.6 Gbps. The read and write ports can support multiple I/O voltage standards. The user-programmable registers enable user to configure the device operation as desired. The device also offers a simple and easy-to-use interface to reduce implementation and debugging efforts, improve time-to-market, and reduce engineering costs.
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