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Cypress Semiconductor Electronic Components Datasheet

CYW54907 Datasheet

IEEE 802.11 a/b/g/n/ac SoC

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PRELIMINARY
CYW54907
WICED™ IEEE 802.11 a/b/g/n/ac SoC with an
Embedded Applications Processor
The Cypress CYW54907 embedded wireless system-on-a-chip (SoC) is uniquely suited for Internet-of-Things (IoT) applications. It
supports all rates specified in the IEEE 802.11a/b/g/n/ac specifications. The device includes an Arm® Cortex®-based applications
processor, a single stream IEEE 802.11ac MAC/baseband/radio, dual-band 5GHz and 2.4GHz transmit power amplifiers (PA), and
receive low-noise amplifiers (LNA). It also supports optional antenna diversity for improved RF performance in difficult environments.
The CYW54907 is an optimized SoC targeting embedded IoT applications in the industrial and medical sensor, home appliance, and
embedded audio markets. Using advanced design techniques and process technology to reduce active and idle power, the device is
designed for embedded applications that require minimal power consumption and a compact size.
The device includes a power management unit (PMU) for simplifying system power topology and allows for direct operation from a
battery while maximizing battery life.
Cypress part numbering scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
Cypress Part Number
BCM54907
CYW54907
BCM54907KWBG
CYW54907KWBG
Features
Applications Processor Features
Arm® Cortex®-R4 32-bit RISC processor.
2 MB of on-chip SRAM for code and data.
An on-chip Cryptography core
640 KB of ROM containing WICED® SDK components such as
RTOS and TCP/IP stack.
17 GPIOs supported.
Q-SPI serial flash interface to support upto 40 Mbps of peak
transfer.
Support for UART, SPI (3), Cypress Serial Control (CSC)-only
(2), and I2S (2) interfaces. (CSC is an I2C-compatible interface.)
Dedicated fractional PLL for audio clock (MCLK) generation.
USB 2.0 host and device modes.
SDIO 3.0 host and device modes
Key IEEE 801.11x Features
IEEE 802.11ac accompliant with 256-QAM
Single-stream spatial multiplexing upto 433.3 Mbps.
Supports 20/40/80 MHz channels with optional SGI.
Full IEEE 802.11 a/b/g/n legacy compatibility with enhanced
performance.
TX and RX low-density parity check (LDPC) support for
improved range and power efficiency.
On-chip power and low-noise amplifiers.
An internal fractional nPLL allows support for a wide range of
reference clock frequencies.
Integrated Arm® Cortex®-R4 processor with tightly coupled
memory for complete WLAN sub system functionality, mini-
mizing the need to wake up the applications processor for
standard WLAN functions (to further minimize power con-
sumption while maintaining the ability to upgrade to future
features in the field).
Software architecture supported by standard WICED® SDK
allows easy migration from existing discrete MCU designs and
to future devices.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-19312 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised Thursday, August 16, 2018


Cypress Semiconductor Electronic Components Datasheet

CYW54907 Datasheet

IEEE 802.11 a/b/g/n/ac SoC

No Preview Available !

PRELIMINARY
CYW54907
Security support:
WPA and WPA2 (Personal) support for powerful encryption
and authentication.
AES and TKIP in hardware for faster data encryption and
IEEE 802.11i compatibility.
Reference WLAN subsystem provides Cisco compatible ex-
tensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, and CCX 5.0).
Wi-Fi Protected Setup and Wi-Fi Easy Setup
■ World wide regulatory support: Global products supported
with worldwide design approval.
General Features
Supports battery voltage range from 3.0 V to 4.8 V with an
internal switching regulator.
Programmable dynamic power management.
6 Kb OTP memory for storing board parameters.
316-bump wafer-level chip-scale package (WLCSP) (4.583
mm × 5.533mm, 0.2mm pitch)
Figure 1. Functional Block Diagram
USB 2.0/
HSIC
SDIO 3.0
PWM (6)
UART (3)
CSC (2)
SPI (2)
GPIO (17)
S/PDIF
or I2S (2)
32 kHz
External LPO
REG_ON
HIB_REG_ON_IN
VBAT
VIO
UART
CSC
PWM
SDIO
SPI
USB
GPIO
JTAG
CYW54907
2 MB RAM,
640 KB ROM
APPS ARM
Cortex-R4
32 KB (I),
32 KB (D)
ICACHE
AXI to AXI
Bridge
Crytography
Engine
TCM
512 KB RAM
320 KB ROM
AXI-to-AXI
Bridge
WLAN
ARM
Cortex-R4
AXI
I2S
Audio
Audio PLL
DMA
RMII/MII
APPS Domain
Always-On Domain
AXI-to-AXI
Bridge
AXI
WLAN
IEEE 802.11ac MAC
1 x 1, IEEE 802.11ac PHY
2.4 GHz and 5 GHz Radio
2.4 GHz
5 GHz
LNA
PA LNA
PA
PS RAM
PS
SR_Eng
PMU
TX
Switch
CSC = Cypress Serial Control. An I2C‐compatible interface.
RF Switch Controls
37.4 MHz Crystal
WRF_PAOUT_5G
WRF_RFIN_5G
WRF_PAOUT_2G
WRF_RFIN_2G
Document Number: 002-19312 Rev. *D
Page 2 of 96


Part Number CYW54907
Description IEEE 802.11 a/b/g/n/ac SoC
Maker Cypress Semiconductor
Total Page 30 Pages
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