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Cypress Semiconductor Electronic Components Datasheet

CYWB0224ABS Datasheet

West Bridge Astoria

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ADVANCE INFORMATION
CYWB0224ABS/CYWB0224ABM
West BridgeTM AstoriaTM
Features
N-Xpress™ NAND Controller Technology
Interleave up to 16 NANDs with 8 Chip Enables (CE#) for
x8 or x16 SLC (CYWB0224ABS) or MLC
(CYWB0224ABM) NAND flash devices.
4-bit Error Correction Coding
www.DataSheet4UB.caodmBlock Management
Static Wear Leveling
Multimedia Device Support
Up to 2 SD/SDIO/MMC/MMC+/CE-ATA devices
SLIM™ Architecture, allowing simultaneous and
independent data paths between the processor and USB,
and between the USB and Mass Storage.
Fully backward compatible (including pin to pin) to Antioch
(CYWB0124AB)
High speed USB at 480 Mbps
USB 2.0 compliant
Integrated USB 2.0 transceiver, smart Serial Interface
Engine
16 programmable endpoints
Flexible Processor Interface, which supports:
Multiplexing and nonMultiplexing Address and Data
interface
SRAM Interface
Pseudo CRAM interface (Antioch Interface)
Pseudo NAND Flash interface
SPI (slave mode) interface
DMA slave support
Ultra low power, 1.8V core operation
Low Power Modes
Small footprint, 6x6mm VFBGA
Supports I2C boot and Processor Boot
Selectable Clock Input Frequencies
19.2 MHz, 24 MHz, 26 MHz, and 48 MHz
Applications
Cellular Phones
Portable Media Players
Personal Digital Assistants
Portable Navigation Devices
Digital Cameras
POS Terminals
Portable Video Recorders
Logic Block Diagram
West BridgeTM AstoriaTM
Control
Registers
uC
Access Control
P
SLIMTM
U
SD/SDIO/ Cypress
MMC+/ CE- N-XpressTM
ATA Block Engine
Configurable Storage
Interface
S
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-11710 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 7, 2007
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Cypress Semiconductor Electronic Components Datasheet

CYWB0224ABS Datasheet

West Bridge Astoria

No Preview Available !

ADVANCE INFORMATION
CYWB0224ABS/CYWB0224ABM
Functional Overview
The SLIM™ architecture
The Simultaneous Link to Independent Multimedia (SLIM)
architecture allows three different interfaces (P-port, S-port and
U-port) to connect to each other independently.
With this architecture, a device using Astoria is connected to a
PC through a USB, without disturbing any of the functions of the
device. The device can still access Mass Storage when the PC
is synchronizing with the main processor.
The SLIM architecture enables new usage models, in which a
www.DataShPeCet4aUc.cceomsses a Mass Storage device independent of the main
processor, or enumerates access to both the Mass Storage and
the main processor at the same time.
In a handset using SLIM architecture, the user can do the
following:
Use the phone as a thumb drive.
Download media files to the phone with all the functionalities
still available on the phone.
Use the same phone as a modem to connect the PC to the
internet.
8051 Microprocessor
The 8051 microprocessor embedded in Astoria does basic
transaction management for all transactions between the P-Port,
S-Port, and the U-Port. The 8051 does not reside in the data
path; it manages the path. The data path is optimized for
performance. The 8051 executes firmware that supports NAND,
SD, SDIO, MMC+, and CE-ATA devices at the S-Port. For the
NAND device, the 8051 firmware follows the Smart Media
algorithm to support the following:
Physical to Logical Management
ECC Correction support
Wear Leveling
NAND Flash bad blocks handling
Configuration and Status Registers
The West Bridge Astoria device includes configuration and
status registers that are accessible as memory-mapped
registers through the processor interface. The configuration
registers allow the system to specify some behaviors of Astoria.
For example, it can mask certain status registers from raising an
interrupt. The status registers convey the status of Astoria, such
as the addresses of buffers for read operations.
Processor Interface (P-Port)
Communication with the external processor is realized through a
dedicated processor interface. This interface is configured to
support different interface standards. This interface supports
multiplexing and nonmultiplexing address or data bus in both
synchronous and asynchronous pseudo CRAM-mapped, and
nonmultiplexing address or data asynchronous SRAM-mapped
memory accesses. The interface may be configured to pseudo
NAND interface to support the processor’s NAND interface. In
addition, this interface may be configured to support the slave
SPI interface. This ensures straightforward electrical communi-
cation with the processor, which may have other devices
connected on a shared memory bus. Asynchronous accesses
can reach a bandwidth of up to 66.7 MBps. Synchronous
accesses are performed at 33 MHz across 16 bits for up to 66.7
MBps bandwidth.
The memory address is decoded to access any of the multiple
endpoint buffers inside Astoria. These endpoints serve as buffers
for data between each pair of ports, for example, between the
processor port and the USB port. The processor writes and reads
into these buffers through the memory interface.
Access to these buffers is controlled by using a DMA protocol or
using an interrupt to the main processor. These two modes are
configured by the external processor.
As a DMA slave, Astoria generates a DMA request signal to
notify the main processor that a specific buffer is ready to be read
from or written to. The external processor monitors this signal
and polls Astoria for the specific buffers ready for a read or write
operation. It then performs the appropriate read or write
operations on the buffer through the processor interface. As a
result, the external processor only deals with the buffers to
access a multitude of storage devices connected to Astoria.
In the Interrupt mode, Astoria communicates important buffer
status changes to the external processor using an interrupt
signal. The external processor then polls Astoria for the specific
buffers ready for read or write, and it performs the appropriate
read or write operations through the processor interface.
USB Interface (U-Port)
In accordance with the USB 2.0 specification, Astoria can
operate in Full-Speed USB mode in addition to High-Speed USB.
The USB interface consists of the USB transceiver. The USB
interface can access and be accessed by both the P-Port and
the S-Port.
The Astoria USB interface supports programmable
CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints.
Mass Storage Support (S-Port)
The S-Port may be configured in three different modes, which
simultaneously support the following:
An SD/SDIO/MMC+/CE-ATA port and a x8 NAND port
Two SD/SDIO/MMC+/CE-ATA ports
Up to eight Chip Enable (CE#) for x8 or x16 NAND flash access
port
These configurations are controlled by the 8051 firmware. The
16-bit NAND interface is used only when there is no other Mass
Storage device connected to the S-Port.
N-Xpress NAND Controller (S-Port)
Astoria, as part of its Mass Storage management functions, can
fully manage the SLC and MLC NAND flash devices. The
embedded 8051 manages the actual reading and writing of the
NAND, along with its required protocols. It performs standard
NAND management functions, such as ECC and wear leveling.
The Astoria supports single bit ECC for the SLC and 4-bit ECC
for MLC NAND flash. SLC NAND flash devices are supported by
CYWB0244ABS. CYWB0244ABM supports both SLC and MLC
NAND flash devices.
Document #: 001-11710 Rev. *A
Page 2 of 6
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Part Number CYWB0224ABS
Description West Bridge Astoria
Maker Cypress Semiconductor
Total Page 6 Pages
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