GVT71256ZC36
Key Features
- Zero Bus Latency, no dead cycles between Write and Read cycles
- Internally synchronized registered outputs eliminate the need to control OE
- Single 3.3V -5% and +5% power supply VCC
- Separate VCCQ for 3.3V or 2.5V I/O
- Single WEN (Read/Write) control pin
- Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications
- Interleaved or linear four-word burst capability
- Individual byte Write (BWa-BWd) control (may be tied LOW)
- CEN pin to enable clock and suspend operations
- Three chip enables for simple depth expansion
