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GVT7C1356A - 256Kx36/512Kx18 Pipelined SRAM

This page provides the datasheet information for the GVT7C1356A, a member of the GVT71256ZC36 256Kx36/512Kx18 Pipelined SRAM family.

Datasheet Summary

Description

The CY7C1354A/GVT71256ZC36 and CY7C1356A/ GVT71512ZC18 SRAMs are designed to eliminate dead cycles when transitioning from Read to Write or vice versa.

These SRAMs are optimized for 100% bus utilization and achieve Zero Bus Latency (ZBL)/No Bus Latency (NoBL).

Features

  • Zero Bus Latency, no dead cycles between Write and Read cycles.
  • Fast clock speed: 200, 166, 133, 100 MHz.
  • Fast access time: 3.2, 3.6, 4.2, 5.0 ns.
  • Internally synchronized registered outputs eliminate the need to control OE.
  • Single 3.3V.
  • 5% and +5% power supply VCC.
  • Separate VCCQ for 3.3V or 2.5V I/O.
  • Single WEN (Read/Write) control pin.
  • Positive clock-edge triggered, address, data, and control signal registers for f.

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Datasheet preview – GVT7C1356A

Datasheet Details

Part number GVT7C1356A
Manufacturer Cypress Semiconductor
File Size 597.12 KB
Description 256Kx36/512Kx18 Pipelined SRAM
Datasheet download datasheet GVT7C1356A Datasheet
Additional preview pages of the GVT7C1356A datasheet.

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Full PDF Text Transcription

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( DataSheet : www.DataSheet4U.com ) CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 166, 133, 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% and +5% power supply VCC • Separate VCCQ for 3.3V or 2.
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