Datasheet Summary
( DataSheet : .. )
CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18
256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture
Features
- Zero Bus Latency, no dead cycles between Write and Read cycles
- Fast clock speed: 200, 166, 133, 100 MHz
- Fast access time: 3.2, 3.6, 4.2, 5.0 ns
- Internally synchronized registered outputs eliminate the need to control OE
- Single 3.3V
- 5% and +5% power supply VCC
- Separate VCCQ for 3.3V or 2.5V I/O
- Single WEN (Read/Write) control pin
- Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications
- Interleaved or linear four-word burst capability
- Individual byte Write (BWa- BWd)...