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Cypress Semiconductor Electronic Components Datasheet

GVT7C1357A Datasheet

(GVT7xxxx) 256K x 36 / 512K x 18 Flow Thru SRAM

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( DataSheet : www.DataSheet4U.com )
1CY7C1357A
CY7C1355A/GVT71256ZB36
PRELIMINARY CY7C1357A/GVT71512ZB18
256Kx36/512Kx18 Flow-Thru SRAM with NoBL™ Architecture
Features
• Zero Bus Latency, no dead cycles between write and
read cycles
• Fast clock speed: 133, 117, and 100 MHz
• Fast access time: 6.5, 7.0, 7.5, and 8.0 ns
• Internally synchronized registered outputs eliminate
the need to control OE
• Single 3.3V –5% and +5% power supply VCC
• Separate VCCQ for 3.3V or 2.5V I/O
• Single R/W (READ/WRITE) control pin
• Positive clock-edge triggered, address, data, and con-
trol signal registers for fully pipelined applications
• Interleaved or linear 4-word burst capability
• Individual byte write (BWa–BWd) control (may be tied
LOW)
• CKE pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• SNOOZE MODE for low power standby
• JTAG boundary scan
• Low profile 119-bump, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The CY7C1355A/GVT71256ZB36 and CY7C1357A/
GVT71512ZB18 SRAMs are designed to eliminate dead cy-
cles when transitions from READ to WRITE or vice versa.
These SRAMs are optimized for 100 percent bus utilization
and achieves Zero Bus Latency (ZBL)/No Bus Latency (No-
BL). They integrate 262,144x36 and 524,288x18 SRAM cells,
respectively, with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. These employ
high-speed, low power CMOS designs using advanced triple-
layer polysilicon, double-layer metal technology. Each memory
cell consists of four transistors and two high valued resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE, CE2, and CE2), Cycle Start Input (ADV/LD),
Clock Enable (CKE), Byte Write Enables (BWa, BWb, BWc,
and BWd), and read-write control (R/W). BWc and BWd apply
to CY7C1355A/GVT71256ZB36 only.
Address and control signals are applied to the SRAM during
one clock cycle, and one cycle later, its associated data oc-
curs, either read or write.
A Clock Enable (CKE) pin allows operation of the
CY7C1355A/CY7C1357A/GVT71256ZB36/GVT71512ZB18
to be suspended as long as necessary. All synchronous inputs
are ignored when (CKE) is HIGH and the internal device reg-
isters will hold their previous values.
There are three Chip Enable pins (CE, CE2, CE2) that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new mem-
ory operation can be initiated and any burst cycle in progress
is stopped. However, any pending data transfers (read or write)
will be completed. The data bus will be in high-impedance
state one cycle after chip is deselected or a write cycle is initi-
ated.
The CY7C1355A/GVT71256ZB36 and CY7C1357A/
GVT71512ZB18 have an on-chip 2-bit burst counter. In the
burst mode, the CY7C1355A/GVT71256ZB36 and
CY7C1357A/GVT71512ZB18 provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the MODE input pin. The MODE pin
selects between linear and interleaved burst sequence. The
ADV/LD signal is used to load a new external address
(ADV/LD=LOW) or increment the internal burst counter
(ADV/LD=HIGH)
Output Enable (OE), Snooze Enable (ZZ) and burst sequence
select (MODE) are the asynchronous signals. OE can be used
to disable the outputs at any given time. ZZ may be tied to LOW
if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Selection Guide
7C1355A-133/
71256ZB36-6.5
7C1357A-133/
71512ZB18-6.5
Maximum Access Time (ns)
6.5
Maximum Operating Current (mA)
410
Maximum CMOS Standby Current (mA)
30
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
7C1355A-117/
71256ZB36-7
7C1357A-117/
71512ZB18-7
7
385
30
7C1355A-100/
71256ZB36-7.5
7C1357A-100/
71512ZB18-7.5
7.5
350
30
7C1355A1-100/
71256ZB36-8
7C1357A1-100/
71512ZB18-8
8
350
30
www.DataSheet4U.com
wwwC.yDparteaSshseSete4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 24, 2001


Cypress Semiconductor Electronic Components Datasheet

GVT7C1357A Datasheet

(GVT7xxxx) 256K x 36 / 512K x 18 Flow Thru SRAM

No Preview Available !

PRELIMINARY
CY7C1355A/GVT71256ZB36
CY7C1357A/GVT71512ZB18
Functional Block Diagram 256Kx36[1]
ZZ
MODE
CKE#
ADV/LD#
R/W#
BWa#, BWb#
BWc#, BWd#
CE#, CE2#, CE2
SA0, SA1, SA
Input
Registers
Address
Control
Control Logic
Mux
Sel
CLK
Output Buffers
OE#
Functional Block Diagram 512Kx18[1]
ZZ
MODE
CKE#
ADV/LD#
R/W#
BWa#, BWb#
CE#, CE2#, CE2
Input
Registers
SA0, SA1, SA
CLK
OE#
DQa-DQd
Address
Control
Control Logic
Mux
Sel
Output Buffers
DQa, DQb
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
2


Part Number GVT7C1357A
Description (GVT7xxxx) 256K x 36 / 512K x 18 Flow Thru SRAM
Maker Cypress Semiconductor
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