DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
CONTENT
1. General Description...................................................................................................... 9
2. Block Diagram............................................................................................................... 9
3. Features....................................................................................................................... 10
4. Pin Configuration........................................................................................................ 12
4.1 Pin Diagram........................................................................................................ 12
4.2 Pin Description .................................................................................................. 13
4.2.1 LED Pins ......................................................................................................... 13
4.2.2 EEPROM Interface.......................................................................................... 15
4.2.3 Clock Interface................................................................................................ 15
4.2.4 Network Interface ........................................................................................... 16
4.2.5 Port 4 MAC MII/RevMII/RMII and PHY MII/RMII Interfaces........................... 17
4.2.6 Port 5 MAC Interfaces .................................................................................... 20
4.2.7 Miscellaneous Pins ........................................................................................ 22
4.2.8 Power Pins...................................................................................................... 23
4.3 Strap Pins Table................................................................................................. 24
5. Control and Status Register Set................................................................................ 26
5.1 Register Table .................................................................................................... 26
5.2 Internal PHY Registers ...................................................................................... 32
5.2.1 Port 0~4 PHY Control Register...................................................................... 32
5.2.2 Port 0~4 PHY Status Register ....................................................................... 33
5.2.3 Port 0~4 PHY Identifier 1 Register ................................................................ 34
5.2.4 Port 0~4 PHY Identifier 2 Register ................................................................ 34
5.2.5 Port 0~4 PHY Auto-Negotiation Advertisement Register............................ 35
5.2.6 Port 0~4 PHY Auto-Negotiation Link Partner Ability Register.................... 36
5.2.7 Port 0~4 PHY Auto-Negotiation Expansion Register .................................. 37
5.2.8 Port 0~4 PHY Specific Control 1 Register .................................................... 38
5.2.9 Port 0~4 PHY Specific Control 2 Register .................................................... 39
5.2.10 Port 0~4 PHY Power Saving Control Register ............................................. 40
5.3 Switch Per-Port Registers................................................................................. 41
5.3.1 Per Port Status Data Register ....................................................................... 41
5.3.2 Per Port Basic Control 0 Register................................................................. 41
5.3.3 Per Port Basic Control 1 Register................................................................. 43
5.3.4 Per Port Block Control 0 Register................................................................. 45
5.3.5 Per Port Block Control 1 Register................................................................. 46
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
2
