74AUP1G07 Description
The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. Pin Assignments The 74AUP1G07 is a single buffer-gate, with an open drain output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF.
74AUP1G07 Key Features
- Advanced Ultra Low Power (AUP) CMOS
- Supply Voltage Range from 0.8V to 3.6V
- 4 mA Output Drive at 3.0V
- Low Static Power Consumption
- Low Dynamic Power Consumption
- IOFF Supports Partial-Power-Down Mode Operation
- ESD Protection Exceeds JESD 22
- Latch-Up Exceeds 100mA per JESD 78, Class I
- Leadless Packages Named per JESD30E
- Totally Lead-Free & Fully RoHS pliant (Notes 1 & 2)