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Diodes Semiconductor Electronic Components Datasheet

PI6CB184Q Datasheet

4-Output PCIe Gen 4 Clock Buffer

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Pb
Lead-free Green
A product Line of
Diodes Incorporated
PI6CB184Q
4-Output PCIe Gen 4 Clock Buffer for Automotive Applications
Features
ÎÎ1.8V supply voltage
ÎÎHCSL input: 100MHz, also suppport 50MHz or 125MHz via
SMBus
ÎÎ4 differential low power HCSL outputs with on-chip
termination
ÎÎIndividual output enable
ÎÎProgrammable Slew rate and output amplitute for each
output
ÎÎDifferential outputs blocked until PLL is locked
ÎÎStrapping pins or SMBus for configuration;
ÎÎ3.3V tolerant SMBus interface support
ÎÎVery low jitter outputs
yyDifferential cycle-to-cycle jitter <50ps
yyDifferential output-to-output skew <50ps
yyPCIe Gen1/Gen2/Gen3/Gen4 compliant
ÎÎAEC-Q 100 qualified, Automotive Grade 2 support
ÎÎTotally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
ÎÎHalogen and Antimony Free. “Green” Device (Note 3)
ÎÎPackaging (Pb-free & Green): 32-lead 5×5mm TQFN
Description
The PI6CB184Q is an 4-output very low power PCIe Gen1/Gen2/
Gen3/Gen4 clock buffer. It takes an reference input to fanout four
100MHz low power differential HCSL outputs with on-chip ter-
minations. The on-chip termination can save 16 external resistors
and make layout easier. Individual OE pin for each output pro-
vides easier power management.
It uses Diodes proprietary PLL design to achieve very low jitter
that meets PCIe Gen1/Gen2/Gen3/Gen4 requirements. Other
than PCIe 100MHz support, this device also support Ethernet
application with 50MHz or 125MHz via SMBus. It provides vari-
ous options such as different slew rate and amplitude through
strapping pins or SMBUS so that users can configure the device
easily to get the optimized performance for their individual
boards. This device is optimized for Automotive designs.
Pin Configuration
Block Diagram
OE[3:0]#
IN+
IN-
PLL
SCLK
SDATA
SADR_TRI
BW_SEL_TRI
PD#
CTRL
LOGIC
BW_SEL_TRI
32 31 30 29 28 27 26 25
1 24
OE2#
NC 2
23 Q2-
NC 3
22 Q2+
Q3
VDD_R
4
GND
21 VDDA
Q2 IN+ 5
20 GNDA
IN- 6
Q1
GND_R
7
Q0
GND_DIG
8
19 Q1-
18 Q1+
17 OE1#
9 10 11 12 13 14 15 16
Notes:      
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.
2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm
antimony compounds.
PI6CB184Q
Document Number DS41705 Rev 1-2
www.diodes.com
January 2019
1 Diodes Incorporated


Diodes Semiconductor Electronic Components Datasheet

PI6CB184Q Datasheet

4-Output PCIe Gen 4 Clock Buffer

No Preview Available !

Pin Description
Pin Number Pin Name
1 BW_SEL_TRI
2 NC
3 NC
4 VDD_R
5 IN+
6 IN-
7 GND_R
8 GND_DIG
9 VDD_DIG
10 SCLK
11 SDATA
12
13
14
15, 26, 30
16, 25
17
18
19
20
21
22
23
24
27
28
29
OE0#
Q0+
Q0-
GND
VDDO
OE1#
Q1+
Q1-
GNDA
VDDA
Q2+
Q2-
OE2#
Q3+
Q3-
OE3#
31 PD#
32 SADR_TRI
A product Line of
Diodes Incorporated
PI6CB184Q
Type
Description
Input
Power
Input
Input
Power
Power
Power
Input
Input/
Output
Input
Output
Output
Power
Power
Input
Output
Output
Power
Power
Output
Output
Input
Output
Output
Input
Input
Input
Tri-level
Latch to select low loop bandwidth, bypass PLL, and high loop band-
width. This pin has both internal pull-up and pull-down
Internal connected for feedback loop. Do not connect this pin
Internal connected for feedback loop. Do not connect this pin
Power supply for input differential buffers
Differential true clock input
Differential complementary clock input
Ground for input differential buffers
Ground for digital circuitry
Power supply for digital circuitry, nominal 1.8V
CMOS SMBUS clock input, 3.3V tolerant
CMOS SMBUS Data line, 3.3V tolerant
CMOS
Active low input for enabling Q0 pair. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
HCSL Differential true clock output
HCSL Differential complementary clock output
Ground
Power supply for differential outputs
CMOS
Active low input for enabling Q1 pair. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
HCSL Differential true clock output
HCSL Differential complementary clock output
Ground for analog circuitry
Power supply for analog circuitry
HCSL Differential true clock output
HCSL Differential complementary clock output
CMOS
Active low input for enabling Q2 pair. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
HCSL Differential true clock output
HCSL Differential complementary clock output
CMOS
Active low input for enabling Q3 pair. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
CMOS
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
Tri-level Latch to select SMBus Address. This pin has an internal pull-down
PI6CB184Q
Document Number DS41705 Rev 1-2
www.diodes.com
January 2019
2 Diodes Incorporated


Part Number PI6CB184Q
Description 4-Output PCIe Gen 4 Clock Buffer
Maker Diodes
Total Page 16 Pages
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