M15T1G1664A-DEBG2CS
Description
The 1Gb Double-Data-Rate-3(L), DDR3(L) DRAM is double data rate architecture to achieve high-speed operation.
Key Features
- Interface and Power Supply
- SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V)
- SSTL_15: VDD/VDDQ = 1.5V(±0.075V)
- JEDEC DDR3(L) pliant
- 8n Prefetch Architecture
- Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS )
- Double-data rate on DQs, DQS and DM
- Data Integrity
- Auto Refresh and Self Refresh Modes
- Power Saving Mode
