M15T1G1664A-DEBG2T Overview
Key Features
- Interface and Power Supply ˗ SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)
- Data Integrity ˗ Auto Refresh and Self Refresh Modes
- Power Saving Mode ˗ Partial Array Self Refresh(PASR) ˗ Power Down Mode
- Signal Synchronization ˗ Write Leveling via MR settings ˗ Read Leveling via MPR
