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M15T4G16256A Datasheet 32M x 16 Bit x 8 Banks DDR3 SDRAM

Manufacturer: ESMT (Elite Semiconductor Microelectronics Technology)

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General Description

The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation.

It is internally configured as an eight-bank DRAM.

The 4Gb chip is organized as 32Mbit x 16 I/Os x 8 bank devices.

Overview

ESMT DDR3(L) SDRAM Feature  Interface and Power Supply ˗ SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3(L) Compliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM  Data Integrity ˗ Auto Refresh and Self Refresh Modes  Power Saving Mode ˗ Partial Array Self Refresh(PASR) ˗ Power Down Mode  Signal Integrity ˗ Configurable DS for system compatibility ˗ Configurable On-Die Termination ˗ ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%) M15T4G16256A (2S) 32M x 16 Bit x 8 Banks DDR3(L) SDRAM  Signal Synchronization ˗ Write Leveling via MR settings ˗ Read Leveling via MPR  Programmable Functions ˗ CAS Latency (5/6/7/8/9/10/11/12/13/14/15/16) ˗ CAS Write Latency (5/6/7/8/9/10/11/12) ˗ Additive Latency (0/CL-1/CL-2) ˗ Write Recovery Time (5/6/7/8/10/12/14/16) ˗ Burst Type (Sequential/Interleaved) ˗ Burst Length (BL8/BC4/BC4 or 8 on the fly) ˗ Self Refresh Temperature Range(Normal/Extended) ˗ Output Driver Impedance (34/40) ˗ On-Die Termination of RTT_Nom(20/30/40/60/120) ˗ On-Die Termination of RTT_WR(60/120) ˗ Precharge Power Down (slow/fast) Ordering Information Product ID Max Freq.

VDD Data Rate (CL-tRCD-tRP) M15T4G16256A–EFBG2S 1066MHz 1.35V / 1.5V DDR3(L)-2133 (14-14-14) M15T4G16256A–DEBG2S 933MHz 1.35V / 1.5V DDR3(L)-1866 (13-13-13) M15T4G16256A–BDBG2S 800MHz 1.35V / 1.5V DDR3(L)-1600 (11-11-11) Package Comments 96 ball BGA 96 ball BGA 96 ball BGA Pb-free Pb-free Pb-free Elite Semiconductor Microelectronics Technology Inc.

Publication Date : Aug.

Key Features

  • and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion. These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages. DDR3(L) SDRAM Addressing Configuration 256Mb x 16 # of Bank 8 Bank Address BA0.

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