| Part number | M55D4G32128A-CDBG2R |
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| Manufacturer | ESMT |
| File Size | 4.41 MB |
| Description | 16M x 32 Bit x 8 Banks LPDDR3 SDRAM |
| Datasheet |
 M55D4G32128A-CDBG2R Datasheet
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| Note |
This datasheet PDF includes multiple part numbers: M55D4G32128A-CDBG2R, M55D4G32128A-GFBG2R. Please refer to the document for exact specifications by model. |
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Ball Name Type CK_t, CK_c Input CKE Input CS_n CA[n:0] DQ[n:0] Input Input I/O DQS[n:0]_t, I/O DQS[n:0]_c DM[n:0] Input ODT Input M55D4G32128A (2R) Function Clock: CK_t and CK_c are differential clock inputs.All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK_t.Single Data Rate (SDR) inputs, CS_n and CKE, are sampled at the positive Clock edge.Clock is defined as the differential pair, CK_t and CK_c.The positive Clock edge is defined by th
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