| Title | |
| Description | Ball Name Type CK_t, CK_c Input CKE Input CS_n CA[n:0] DQ[n:0] Input Input I/O DQS[n:0]_t, I/O DQS[n:0]_c DM[n:0] Input ODT Input M55D4G32128A (2R) Function Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK_t. Single Data Rate (SDR) inputs, CS_n and CKE, are sampled at the positive Clock edge... |
| Features |
Ultra-low-voltage core and I/O power supplies VDD1 = 1.70 –1.95V VDD2, VDDCA, VDDQ = 1.14 –1.30V Organization 16M words x 32 bits x 8 banks JEDEC LPDDR3-compliant 4KB page size Row address: R0 to R13 Column address: C0 to C9 (x32 bits) Auto precharge option for each burst access Eight-bit prefetch DDR architecture Eight intern... |
| Datasheet |
 M55D4G32128A-GFBG2R Datasheet - 4.41MB |
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