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EDD2504AKTA-E - 256M bits DDR SDRAM (64M words x 4 bits)

General Description

The EDD2504AKTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 16,777,216 words × 4 bits × 4 banks.

Read and write operations are performed at the cross points of the CK and the /CK.

This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture.

Key Features

  • Power supply : VDDQ = 2.5V ± 0.2V : VDD = 2.5V ± 0.2V.
  • Data rate: 333Mbps/266Mbps (max. ).
  • Double Data Rate architecture; two data transfers per clock cycle.
  • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver.
  • Data inputs, outputs, and DM are synchronized with DQS.
  • 4 internal banks for concurrent operation.
  • DQS is edge aligned with data for READs; center aligned with dat.

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Datasheet Details

Part number EDD2504AKTA-E
Manufacturer Elpida Memory
File Size 597.61 KB
Description 256M bits DDR SDRAM (64M words x 4 bits)
Datasheet download datasheet EDD2504AKTA-E Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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( DataSheet : www.DataSheet4U.com ) DATA SHEET 256M bits DDR SDRAM EDD2504AKTA-E (64M words × 4 bits) Description The EDD2504AKTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 16,777,216 words × 4 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. It is packaged in 66-pin plastic TSOP (II). Pin Configurations /xxx indicates active low signal.