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EDD2508AETA - (EDD2508AETA / EDD2516AETA) 256M bits DDR SDRAM

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Elpida Memory

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EDD2508AETA (EDD2508AETA / EDD2516AETA) 256M bits DDR SDRAM by Elpida Memory - Datasheet Preview — Datasheet preview – EDD2508AETA

Datasheet Details

Part number	EDD2508AETA
Manufacturer	Elpida Memory
File Size	648.64 KB
Description	(EDD2508AETA / EDD2516AETA) 256M bits DDR SDRAM
Datasheet	EDD2508AETA Datasheet
Additional preview pages of the EDD2508AETA datasheet.

Product details

Features

Double-data-rate architecture; two data transfers per clock cycle.
The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture.
Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver.
Data inputs, outputs, and DM are synchronized with DQS.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL.

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Published: Aug 14, 2008 |