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Exar Corporation

XRT73L02M Datasheet Preview

XRT73L02M Datasheet

TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

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XRT73L02M
MAY 2003
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
GENERAL DESCRIPTION
The XRT73L02M is a two-channel fully integrated
Line Interface Unit (LIU) for E3/DS3/STS-1 applica-
tions. It incorporates independent Receivers, Trans-
mitters in a single 100 pin TQFP package.
The XRT73L02M can be configured to operate in ei-
ther E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1
(51.84 MHz) modes.The transmitter can be turned off
or tri-stated for redundancy support and for conserv-
ing power.
The XRT73L02M’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of ca-
ble attenuation.
The XRT73L02M provides both Serial Microproces-
sor Interface as well as Hardware mode for program-
ming and control.
The XRT73L02M supports local,remote and digital
loop-backs. The XRT73L02M also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
FEATURES
RECEIVER:
On chip Clock and Data Recovery circuit for high
input jitter tolerance.
Meets the jitter tolerance requirements as specified
in ITU-T G.823_1993 for E3 and Telcordia GR-499-
CORE for DS3 applications.
Detects and Clears LOS as per G.775.
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
On chip B3ZS/HDB3 encoder and decoder that can
either be enabled or disabled.
On-chip clock synthesizer generates the appropri-
ate rate clock from a single frequency XTAL.
Provides low jitter clock outputs for either DS3,E3
or STS-1 rates.
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
Provides low jitter output clock.
TRANSMITTER:
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
Tri-state Transmit output capability for redundancy
applications
Transmitter can be turned on or off.
CONTROL AND DIAGNOSTICS:
5 wire Serial Microprocessor Interface for control
and configuration.
Supports optional internal Transmit Driver Monitor-
ing.
PRBS error counter register to accumulate errors.
Hardware Mode for control and configuration.
Supports Local, Remote and Digital Loop-backs.
Single 3.3 V ± 5% power supply.
5 V Tolerant I/O.
Available in 100 pin TQFP.
-40°C to 85°C Industrial Temperature Range.
APPLICATIONS
E3/DS3 Access Equipment.
STS1-SPE to DS3 Mapper.
DSLAMs.
Digital Cross Connect Systems.
CSU/DSU Equipment.
Routers.
Fiber Optic Terminals.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




Exar Corporation

XRT73L02M Datasheet Preview

XRT73L02M Datasheet

TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

No Preview Available !

XRT73L02M
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
xr
FIGURE 1. BLOCK DIAGRAM OF THE XRT 73L02M
SDI
SDO
INT
SClk
CS
RESET
HOST/HW
STS-1/DS3
E3
REQEN
RTIP
RRING
SR/DR
LLB
TTIP
TRING
MTIP
MRING
DMO
Serial
Processor
Interface
XRT75L03
Peak Detector
AGC/
Equalizer
Slicer
Local
LoopBack
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
MUX
Remote
LoopBack
Invert
HDB3/
B3ZS
Decoder
Line
Driver
Device
Monitor
Tx
Pulse
Shaping
Tx
Control
Timing
Control
HDB3/
MUX B3ZS
Encoder
CLK_OUT
E3Clk,DS3Clk,
STS-1Clk
RLOL
RxON
RxClkINV
RxClk
RPOS
RNEG/
LCV
RLB
RLOS
TPOS
TNEG
TxClk
TAOS
TxLEV
TxON
Note: Serial Processor Interface input pins are shared by in "Host" Mode and redefined in the "Hardware" Mode.
TRANSMIT INTERFACE CHARACTERISTICS
Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal
to the line
Integrated Pulse Shaping Circuit.
Built-in B3ZS/HDB3 Encoder (which can be dis-
abled).
Accepts Transmit Clock with duty cycle of 30%-
70%.
Generates pulses that comply with the ITU-T G.703
pulse template for E3 applications.
Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499-CORE
and ANSI T1.102_1993.
Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253-
CORE.
Transmitter can be turned off in order to support
redundancy designs.
RECEIVE INTERFACE CHARACTERISTICS
Integrated Adaptive Receive Equalization for opti-
mal Clock and Data Recovery.
Declares and Clears the LOS defect per ITU-T
G.775 requirements for E3 and DS3 applications.
Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 for E3 Applications.
Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE for DS3 Applications.
Declares Loss of Signal (LOS) and Loss of Lock
(LOL) Alarms.
Built-in B3ZS/HDB3 Decoder (which can be dis-
abled).
Recovered Data can be muted while the LOS Con-
dition is declared.
Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment.
2


Part Number XRT73L02M
Description TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
Maker Exar Corporation
Total Page 30 Pages
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