XRT73L03B Datasheet | Exar

DESCRIPTION The XRT73L03B, 3-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L03A and consists of three independent line transmitters and receivers integrated on a single chip designed for DS3, E3 or SONET STS-1 applications. Each channel of the XRT73L03B can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) rates. Each channel can be configured to operate in a mode/data rate that is independent of the other channels. In the transmit direction, each channel encodes input data to either B3ZS (DS3/STS-1) or HDB3 (E3) format and converts the data into the appropriate pulse shapes for transmission over coaxial cable via a 1:1 transformer. In the receive direction, the XRT73L03B performs equalization on ining signals, performs Clock Recovery, decodes data from either B3ZS or HDB3 format, converts the receive data into TTL/CMOS format, checks for LOS or LOL conditions and detects and declares the occurrence of Line Code Violations. FEATURES - Incorporates an improved Timing Recovery circuit and is pin and functional patible to XRT73L03A - Meets E3/DS3/STS-1 Jitter Tolerance Requirements - Contains a 4-Wire Microprocessor Serial Interface - Full Loop-Back Capability - Transmit and Receive Power Down Modes - Full Redundancy Support - Uses Minimum External ponents - Single +3.3V Power Supply - Low power CMOS design - 5V tolerant I/O - -40°C to +85°C Operating Temperature Range - Available in a 120 pin LQFP package APPLICATIONS - Digital Cross Connect Systems - CSU/DSU Equipment - Routers - Fiber Optic Terminals - Multiplexers - ATM Switches FIGURE 1. XRT73L03B BLOCK DIAGRAM E3_(n) STS-1/DS3_(n) Host/(HW) RLOL_(n) EXClk_(n) Rx OFF Rx Clk INV RTIP_(n) RRing_(n) REQEN_(n) AGC/ Equalizer Peak Detector Slicer Clock Recovery Data Recovery Invert Rx Clk_(n) LOSTHR_(n) SDI SDO SClk CS REGR Serial Processor Interface LOS Detector HDB3/ B3ZS Decoder RPOS_(n) RNEG_(n) LCV_(n) ENDECDIS RLOS_(n)...