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Exar Corporation

XRT79L72 Datasheet Preview

XRT79L72 Datasheet

2-CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
XRT79L72
FEBRUARY 2005
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
REV. P1.0.2
HARDWARE MANUAL
The XRT79L72 is a two channel, ATM UNI/PPP
Physical Layer Processor with integrated DS3/E3
framing controllers and Line Interface Units with Jitter
Attenuators that are designed to support ATM direct
mapping and cell delineation as well as PPP mapping
and Frame processing. For ATM UNI applications,
this device provides the ATM Physical Layer (Physi-
cal Medium Dependent and Transmission Conver-
gence sub-layers) interface for the public and private
networks at DS3/E3 rates. For Clear-Channel Framer
applications, this device supports the transmission
and reception of “user data” via the DS3/E3 payload.
The XRT79L72 includes DS3/E3 Framing, Line Inter-
face Unit with Jitter Attenuator that supports mapping of
ATM or HDLC framed data. A flexible parallel micropro-
cessor interface is provided for configuration and con-
trol. Industry standard UTOPIA II and POS-PHY inter-
face are also provided.
GENERAL FEATURES:
Integrated T3/E3 Line Interface Unit
Integrated Jitter Attenuator that can be selected
either in Receive or Transmit path
Flexible integrated Clock Multiplier that takes single
frequency clock and generates either DS3 or E3
frequency.
8/16 bit UTOPIA Level I and II and PPP Multi-PHY
Interface operating at 25, 33 or 50 MHz.
HDLC Controller that provides the mapping/extrac-
tion of either bit or byte mapped encapsulated
packet from DS3/E3 Frame.
Contains on-chip 16 cell FIFO (configurable in
depths of 4, 8, 12 or 16 cells), in both the Transmit
(TxFIFO) and Receive Directions (RxFIFO)
Contains on-chip 54 byte Transmit and Receive
OAM Cell Buffer for transmission, reception and
processing of OAM Cells
Supports ATM cell or PPP Packet Mapping
Supports M13 and C-Bit Parity Framing Formats
Supports DS3/E3 Clear-Channel Framing.
Includes PRBS Generator and Receiver
Supports Line, Cell, and PLCP Loop-backs
Interfaces to 8 Bit wide Intel, Motorola or PowerPC
Low power 3.3V, 5V Input Tolerant, CMOS
Available in 456 Lead PBGA Package
JTAG Interface
LINE INTERFACE UNIT
On chip Clock and Data Recovery circuit for high
input jitter tolerance
Meets E3/DS3 Jitter Tolerance Requirements
Detects and Clears LOS as per G.775.
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
Meets ETSI TBR 24 and GR-499 Jitter Transfer
Requirements
On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
On chip advanced crystal-less Jitter Attenuator
Jitter Attenuator can be selected in Receive or
Transmit paths
16 or 32 bits selectable FIFO size
Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards
Jitter Attenuator can be disabled
Maximum power consumption 1.7W
DS3/E3 FRAMER
DS3 framer supports both M13 and C-bit parity.
DS3 framer meets ANSI T1.107 and T1.404 stan-
dards.
Detects OOF,LOF,AIS,RDI/FERF alarms.
Generation and Insertion of FEBE on received par-
ity errors supported.
Automatic insertion of RDI/FERF on alarm status.
E3 framer meets G.832,G.751 standards.
Framers can be bypassed.
ATM/PPP PROTOCOL PROCESSOR
TRANSMIT CELL PROCESSING
Extracts ATM cells
Supports ATM cell payload scrambling
Maps ATM cells into E3 or DS3 frame
PLCP frame and mapping of ATM cell streams
RECEIVE CELL PROCESSING
Extraction of ATM cells from PLCP frame or directly
from E3 or DS3 frame
Termination of PLCP frame
Supports payload cell de-scrambling
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




Exar Corporation

XRT79L72 Datasheet Preview

XRT79L72 Datasheet

2-CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

No Preview Available !

XRT79L72
REV. P1.0.2
PRELIMINARY
xr
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
TRANSMIT PACKET PROCESSING
Inserts PPP packets into data stream
Maps HDLC data stream directly into DS3 or E3 frame
Extracts in-band messaging packets
Supports CRC-16/32, HDLC flag and Idle sequence generation
RECEIVE PACKET PROCESSING
Extracts HDLC data stream from DS3 or E3 frame
Inserts in-band messaging packets
Detects and removes HDLC flags
UTOPIA/ SYSTEM INTERFACE
8/16 bit UTOPIA Level I and II and PPP Multi-PHY Interface operating at 25, 33 or 50 MHz.
Compliant with ATM Forum UTOPIA II interface
Programmable FIFO size for both Transmit and Receive direction
Compliant to POS-PHY Level 2 interface
SERIAL INTERFACE
Serial clock and data interface for accessing DS3/E3 framer
Serial clock and data interface for accessing cell/packet processor
APPLICATIONS
Digital Access and Cross Connect Systems
3G Base Stations
DSLAMs
Digital, ATM, WAN and LAN Switches
FIGURE 1. BLOCK DIAGRAM OF THE XRT79L72
RTIP
RRING
Channel 1 of 2
AGC/
Equalizer
TU-3
PCOloHck &
ProceDsastoar
Recov ery
Receiver Block
Jitter
Attenuator
Rx DS3/
E3
Framer
TTIP
TRING
E3CLK
DS3CLK
ClkIN
12.288
MHz
Pulse
Shaper
Timing
Control
Transmitter Block
Clock
Synthesizer
Jitter
Attenuator
Tx DS3/
E3
Framer
Microprocessor Interface
PLCP &
Overhead
HDLC
Controller
PLCP &
Overhead
HDLC
Controller
ATM Cell
Processor
or PPP
Processor
UTOPIA/
POS-PHY
Interface
ATM Cell
Processor
or PPP
Processor
2
UTOPIA/
POS-PHY
Interface
JTAG Test Port
Receive
Utopia
POS-PHY
Interface
Transmit
Utopia
POS-PHY
Interface
2


Part Number XRT79L72
Description 2-CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
Maker Exar Corporation
Total Page 30 Pages
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