octal d-type flip-flop.
s Ideal for addressable register applications s Clock enable for address and data synchronization applications s Eight edge-triggered D-type flip-flops s Buffered common .
s Clock enable for address and data synchronization applications s Eight edge-triggered D-type flip-flops s Buffered com.
The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The stat.
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