900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Fairchild Semiconductor Electronic Components Datasheet

74AC74 Datasheet

Dual D-Type Positive Edge-Triggered Flip-Flop

No Preview Available !

January 2008
74AC74, 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
Features
ICC reduced by 50%
Output source/sink 24mA
ACT74 has TTL-compatible inputs
General Description
The AC/ACT74 is a dual D-type flip-flop with Asynchro-
nous Clear and Set inputs and complementary (Q, Q)
outputs. Information at the input is transferred to the out-
puts on the positive edge of the clock pulse. Clock trig-
gering occurs at a voltage level of the clock pulse and is
not directly related to the transition time of the positive-
going pulse. After the Clock Pulse input threshold volt-
age has been passed, the Data input is locked out and
information present will not be transferred to the outputs
until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and
Q HIGH
Ordering Information
Order Number
74AC74SC
74AC74SJ
74AC74MTC
74AC74PC
74ACT74SC
74ACT74SJ
74ACT74MTC
74ACT74PC
Package
Number
M14A
M14D
MTC14
N14A
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
www.fairchildsemi.com


Fairchild Semiconductor Electronic Components Datasheet

74AC74 Datasheet

Dual D-Type Positive Edge-Triggered Flip-Flop

No Preview Available !

Connection Diagram
Logic Symbols
Pin Descriptions
Pin Names
D1, D2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q1, Q2, Q2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
IEEE/IEC
Truth Table
(Each Half)
Inputs
Outputs
SD CD CP D Q
L H XXH
Q
L
H L XXL H
L L XXH H
HH
HH
L
HH
LL
H
H H L X Q0 Q0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Q0 (Q0) = Previous Q (Q) before LOW-to-HIGH Transition of Clock
©1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Rev. 1.6.1
2
www.fairchildsemi.com


Part Number 74AC74
Description Dual D-Type Positive Edge-Triggered Flip-Flop
Maker Fairchild Semiconductor
Total Page 13 Pages
PDF Download

74AC74 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 74AC74 DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
STMicroelectronics
2 74AC74 Dual D-Type Positive Edge-Triggered Flip-Flop
Fairchild Semiconductor





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy