74ACT16240 Datasheet | Fairchild Semiconductor

Description The ACT16240 contains sixteen inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. Features s Separate control logic for each byte s 16-bit version of the ACT240 s Outputs source/sink 24 m A s TTL-patible inputs Ordering Code: Order Number 74ACT16240SSC 74ACT16240MTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram .. Pin Descriptions Pin Names OEn I0- I15 O0- O15 Description Output Enable Inputs (Active LOW) Inputs Outputs FACT- is a trademark of Fairchild Semiconductor Corporation. © 2005 Fairchild Semiconductor Corporation DS500293 .fairchildsemi. Truth Tables Inputs OE1 L L H I0- I3 L H X Outputs O0- O3 H L Z OE2 L L H Inputs I4- I7 L H X Outputs O4- O7 H L Z Inputs OE3 L L H I8- I11 L H X Outputs O8- O11 H L Z OE4 L L H Inputs I12- I15 L H X Outputs O12- O15 H L Z H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Functional Description The ACT16240 contains sixteen inverting buffers with 3-STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independently of the other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. Logic Diagram .fairchildsemi. Absol...