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Fairchild Semiconductor Electronic Components Datasheet

74LVTH16500 Datasheet

Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary

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74LVTH16500 pdf
Preliminary
May 2000
Revised May 2000
74LVTH16500
Low Voltage 18-Bit Universal Bus Transceivers
with 3-STATE Outputs (Preliminary)
General Description
The LVTH16500 is an 18-bit universal bus transceiver
combining D-type latches and D-type flip-flops to allow
data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
The LVTH16500 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The transceiver is designed for low voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH16500 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 16500
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVTH16500MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVTH16500MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS012447
www.fairchildsemi.com


Fairchild Semiconductor Electronic Components Datasheet

74LVTH16500 Datasheet

Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary

No Preview Available !

74LVTH16500 pdf
Preliminary
Connection Diagram
Functional Description
For A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A
data is latched if CLKAB is held at a HIGH or LOW logic
level. If LEAB is LOW, the A bus data is stored in the latch/
flip-flop on the HIGH-to-LOW transition of CLKAB. Output-
enable OEAB is active-HIGH. When OEAB is HIGH, the
Logic Diagram
Pin Descriptions
Pin Names
Description
A1A18
Data Register A Inputs/3-STATE Outputs
B1B18
Data Register B Inputs/3-STATE Outputs
CLKAB, CLKBA Clock Pulse Inputs
LEAB, LEBA Latch Enable Inputs
OEAB, OEBA Output Enable Inputs
Function Table (Note 1)
OEAB
Inputs
LEAB CLKAB
A
Output
B
LXXX
Z
HHX L
L
HHXH
H
HLL
L
HL H
H
H L H X B0 (Note 2)
H L L X B0 (Note 3)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
↓ = HIGH-to-LOW Clock Transition
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, and CLKBA.
Note 2: Output level before the indicated steady-state input conditions
were established.
Note 3: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was LOW before LEAB went LOW.
outputs are active. When OEAB is LOW, the outputs are in
the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active-HIGH and OEBA is active-
LOW).
www.fairchildsemi.com
2


Part Number 74LVTH16500
Description Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs Preliminary
Maker Fairchild Semiconductor
Total Page 7 Pages
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