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74LVTH32373 Datasheet

Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary)

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74LVTH32373 pdf
Preliminary
August 2001
Revised August 2001
74LVT32373 74LVTH32373
Low Voltage 32-Bit Transparent Latch
with 3-STATE Outputs (Preliminary)
General Description
The LVT32373 and LVTH32373 contain thirty-two non-
inverting latches with 3-STATE outputs and are intended
for bus oriented applications. The device is byte controlled.
The flip-flops appear transparent to the data when the
Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the setup time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the outputs are in a high impedance state.
The LVTH32373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These latches are designed for low-voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT32373 and LVTH32373
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH32373),
also available without bushold feature (74LVT32373)
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s ESD performance:
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
(Preliminary)
Ordering Code:
Order Number Package Number
Package Description
74LVT32373GX
(Note 1)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
74LVTH32373GX
(Note 1)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
Note 1: BGA package available in Tape and Reel only.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500548
www.fairchildsemi.com


Fairchild Semiconductor Electronic Components Datasheet

74LVTH32373 Datasheet

Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary)

No Preview Available !

74LVTH32373 pdf
Preliminary
Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
LEn
I0–I31
O0–O31
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
3-STATE Outputs
FBGA Pin Assignments
(Top Thru View)
123456
A O1 O0 OE1 LE1 I0
I1
B O3 O2 GND GND I2
I3
C
O5
O4 VCC1 VCC1
I4
I5
D O7 O6 GND GND I6
I7
E O9 O8 GND GND I8
I9
F O11 O10 VCC1 VCC1 I10 I11
G O13 O12 GND GND I12 I13
H
O14 O15 OE2 LE2
I15
I14
J
O17 O16 OE3 LE3
I16
I17
K O19 O18 GND GND I18 I19
L O21 O20 VCC2 VCC2 I20 I21
M O23 O22 GND GND I22 I23
N O25 O24 GND GND I24 I25
P O27 O26 VCC2 VCC2 I26 I27
R O29 O28 GND GND I28 I29
T
O30 O31 OE4 LE4
I31
I30
Truth Table
Inputs
CP1
OE1
I0I7
XH
X
HL
L
HL
H
LL
X
Inputs
CP3
OE3
I16I23
XH
X
HL
L
HL
H
LL
X
H = HIGH Voltage Level L = LOW Voltage Level
Outputs
O0O7
Z
L
H
O0
Outputs
CP2
X
H
H
L
O16O23
CP4
ZX
LH
HH
O0
X = Immaterial
L
Z = HIGH Impedance
Inputs
Outputs
OE2
H
L
L
L
Inputs
I8I15
X
L
H
X
O8O15
Z
L
H
O0
Outputs
OE4
I24I31
O24O31
HX
Z
LL
L
LH
H
LX
O0
Oo = Previous Oo prior to HIGH-to-LOW transition of LE
Functional Description
The LVT32373 and LVTH32373 contain thirty-two D-type latches with 3-STATE standard outputs. The device is byte con-
trolled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full
32-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn
enters the latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input
changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LEn. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn
is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into the latches.
www.fairchildsemi.com
2


Part Number 74LVTH32373
Description Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary)
Maker Fairchild Semiconductor
Total Page 6 Pages
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