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CD4027BCN - Dual J-K Master/Slave Flip-Flop

This page provides the datasheet information for the CD4027BCN, a member of the CD4027BC Dual J-K Master/Slave Flip-Flop family.

Datasheet Summary

Description

The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors.

Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs.

Features

  • s Wide supply voltage range: s High noise immunity: 3.0V to 15V 0.45 VDD (typ. ) s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s Low power: 50 nW (typ. ) s Medium speed operation: 12 MHz (typ. ) with 10V supply Ordering Code: Order Number CD4027BCM CD4027BCN Package Number M16A N16E Package.

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Datasheet preview – CD4027BCN

Datasheet Details

Part number CD4027BCN
Manufacturer Fairchild Semiconductor
File Size 56.43 KB
Description Dual J-K Master/Slave Flip-Flop
Datasheet download datasheet CD4027BCN Datasheet
Additional preview pages of the CD4027BCN datasheet.

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Full PDF Text Transcription

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CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset October 1987 Revised January 1999 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edge sensitive to the clock input and change state on the positive-going transition of the clock pulses. Set or reset is independent of the clock and is accomplished by a high level on the respective input. All inputs are protected against damage due to static discharge by diode clamps to VDD and VSS.
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