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DM74ALS138 - 3 to 8 Line Decoder/Demultiplexer

General Description

These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times.

In high-performance memory systems these decoders can be used to minimize the effects of system decoding.

Key Features

  • fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design. Features s Designed specifically for high speed: Memory decoders Data transmission systems s 3- to 8-line decoder incorporates 3 enable inputs to simplify cascading and/or data reception s Low power dissipation…23 mW typ s Switching specifications guaranteed over full temperature and VCC range s Advan.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DM74ALS138 3 to 8 Line Decoder/Demultiplexer September 1986 Revised February 2000 DM74ALS138 3 to 8 Line Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The DM74ALS138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs.