DM74LS109A Datasheet - Fairchild Semiconductor

Dual Positive-Edge-Triggered J-K Flip-Flop

DM74LS109A General Description

This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge .

DM74LS109A Datasheet (52.34 KB)

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DM74LS109A

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Fairchild Semiconductor

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52.34 KB

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Dual positive-edge-triggered j-k flip-flop.
DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs June 1986 Revised March 2000 DM74LS109A Dual Pos.

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DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop Fairchild Semiconductor

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DM74LS109A General Description

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