FDC6321C Datasheet, Fairchild Semiconductor

N-Ch 25 V, 0.68 A, RDS(ON) = 0.45 Ω @ VGS= 4.5 V P-Ch -25 V, -0.46 A, RDS(ON) = 1.1 Ω @ VGS= -4.5 V. Very low level gate drive requirements allowing direct operation in 3.

as a replacement for digital transistors in load switching applications. Since bias resistors are not required this dual.

These dual N & P Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This.