Download FDMA507PZ Datasheet PDF
Fairchild Semiconductor
FDMA507PZ
Features - Max r DS(on) = 24 mΩ at VGS = -5 V, ID = -7.8 A - Max r DS(on) = 25 mΩ at VGS = -4.5 V, ID = -7 A - Max r DS(on) = 35 mΩ at VGS = -2.5 V, ID = -5.5 A - Max r DS(on) = 45 mΩ at VGS = -1.8 V, ID = -4 A - Low Profile - 0.8 mm maximum - in the package Micro FET 2X2 mm - HBM ESD protection level > 3.2K V typical (Note3) - Free from halogenated pounds and antimony oxides - Ro HS pliant General Description This device is designed specifically for battery charge or load switching in cellular handset and other ultraportable applications. It features a MOSFET with low on-stade resistance. The Micro FET 2X2 package offers exceptional thermal perfomance for its physical size and is well suited to linear mode applications. MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS VGS ID Parameter Drain to Source Voltage Gate to Source Voltage Drain Current -Continuous -Pulsed PD TJ, TSTG Power Dissipation Power Dissipation TA = 25 °C TA = 25 °C (Note 1a) (Note 1b) TA = 25 °C (Note...