FQD2P40 Datasheet | Fairchild Semiconductor

Description These P-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand a high energy pulse in the avalanche and mutation modes. These devices are well suited for electronic lamp ballasts based on the plementary half bridge topology. Features - - - - - - -1.56A, -400V, RDS(on) = 6.5Ω @VGS = -10 V Low gate charge ( typical 10 n C) Low Crss ( typical 6.5 p F) Fast switching 100% avalanche tested Improved dv/dt capability S D G! ! - - ▶ ▲ - G D-PAK FQD Series I-PAK FQU Series ! Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) Drain Current - Pulsed (Note 1) FQD2P40 / FQU2P40 -400 -1.56 -0.98 -6.24 ± 30 (Note 2) (Note 1) (Note 1) (Note 3) Units V A A A V m J A m J V/ns W W W/°C °C °C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA = 25°C) - Power Dissipation (TC = 25°C) 120 -1.56 3.8 -4.5 2.5 38 0.3 -55 to +150 300 TJ, TSTG TL - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8” from case for 5 seconds Thermal Characteristics Symbol RθJC RθJA RθJA Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient - Thermal Resistance, Junction-to-Ambient Typ ---Max 3.29 50 110 Units °C/W °C/W °C/W - When mounted on the minimum pad size remended (PCB...