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DSP56858 - 16-bit Digital Signal Controllers

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General Description

• 120 MIPS at 120MHz • 40K x 16-bit Program SRAM • 24K x 16-bit Data SRAM • 1K x 16-bit Boot ROM • Access up to 2M words of program memory or 8M data memory • Chip Select Logic for glue-less interface to ROM and SRAM • Six (6) independent channels of DMA • Two (2) Enhanced Synchronous Serial Interfaces (ESSI) • Two (2) Serial Communication Interfaces (SCI) • Serial Port Interface (SPI) • 8-bit Parallel Host Interface • General Purpose 16-bit Quad Timer • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Computer Operating Properly (COP)/Watchdog Timer • Time-of -Day (TOD) • 144 LQFP and 144 MAPBGA packages • Up to 47 GPIO 6 VDDIO 12 VDD 8 VSSIO 14 VSS VDDA 8 VSSA 2 JTAG/ Enhanced OnCE Program Controller and Hardware Looping Unit Address Generation Unit 16-Bit 56800E Core Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Bit Manipulation Unit www.DataSheet4U.com PAB PDB CDBR CDBW Memory Program Memory 40,960 x 16 SRAM Boot ROM 1024 x 16 ROM Data Memory 24,576 x 16 SRAM XDB2 XAB1 XAB2 PAB PDB CDBR CDBW System Bus Control DMA 6 channel Core CLK IPBus Bridge (IPBB) IPWDB Decoding Peripherals A0-20 [20:0] D0-D15 [15:0] RD Enable WR Enable CS0-CS3[3:0] or GPIOA0-A3 Bus Control External Address Bus Switch External Data Bus Switch External Bus Interface Unit 2 SCI ESSI0 or or GPIOE GPIOC IPRDB IPAB DMA Requests IPBus CLK POR CLKO 3 MODE A-C or GPIOH0-H2 System COP/TOD CLK Integration Module RSTO RESET ESSI1 or GPIOD Quad Timer or GPIOG 4 SPI Host Interrupt or Interface Controller GPIOF or GPIOB 4 16 IRQA IRQB COP/ Watchdog Time of Day Clock Generator OSC PLL EXTAL XTAL 4 6 6 56858 Block Diagram 56858 Technical Data, Rev.

6 Freescale Semiconductor 3 Part 1 Overview 1.1 56858

Overview

56858 Data Sheet Technical Data www.DataSheet4U.com 56800E 16-bit Digital Signal Controllers DSP56858 Rev.

6 01/2007 freescale.com www.DataSheet4U.

Key Features

  • 1.1.1.
  • Digital Signal Processing Core Efficient 16-bit engine with dual Harvard architecture 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Four (4) 36-bit accumulators including extension bits 16-bit bidirectional shifter Parallel instruction set with uni.

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