Description
120 MIPS at 120MHz - 16K x 16-bit Program SRAM - 16K x 16-bit Data SRAM - 1K x 16-bit Boot ROM - Access up to 2M words of program or 8M data memory - Chip Select Logic for glue-less interface to ROM and SRAM - Six (6) independent channels of DMA - Enhanced Synchronous Serial Interfaces (ESSI) - Two (2) Serial munication Interfaces (SCI) - Serial Port Interface (SPI) - 8-bit Parallel Host Interface - General Purpose 16-bit Quad Timer - JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging - puter Operating Properly (COP)/Watchdog Timer - Time-of-Day (TOD) - 128 LQFP package - Up to 41 GPIO 6 VDDIO 11 VDD 6 VSSIO 10 VSS VDDA 6 VSSA JTAG/ Enhanced OnCE Program Controller and Hardware Looping Unit Address Generation Unit 16-Bit DSP56800E Core Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Bit Manipulation Unit.
Key Features
- Memory Harvard architecture permits up to three (3) simultaneous accesses to program and data memory On-Chip Memory
- 16K × 16-bit Program SRAM
- 16K × 16-bit Data SRAM
- 1K × 16-bit Boot ROM
- Off-Chip Memory Expansion (EMI)
- Access up to 2M words of program memory or up to 8M words of data memory
- Chip Select Logic for glue-less interface to ROM and SRAM 1.1.3
