DSP56858
Description
Six (6) independent channels of DMA 8-bit Parallel Host Interface* Time-of-Day (TOD) Up to 47 GPIO * Each peripheral I/O can be used alternately as a GPIO if not needed 1.1.4 - - Energy Information Fabricated in high-density CMOS with 3.3V, TTL-pa.
Key Features
- Memory Harvard architecture permits up to three (3) simultaneous accesses to program and data memory On-Chip Memory
- 40K × 16-bit Program RAM
- 24K × 16-bit Data RAM
- 1K × 16-bit Boot ROM
- Off-Chip Memory Expansion (EMI)
- Access up to 2M words of program or 8M data memory (using chip selects)
- Chip Select Logic for glue-less interface to ROM and SRAM 1.1.3
