* 16-Bit S12 CPU, 32 kByte FLASH, 2.0 kByte RAM
* Background Debug (BDM) & Debug Module (DBG)
* Die to Die bus interface for transparent memory mapping
* On-chip oscillator & two independent watchdogs
* LIN 2.1 Physical Layer Interface with integrated SCI
MM912F634
Freescale Semiconductor
4.47 MB
Integrated s12 based relay driver.
Freescale Semiconductor Advanced Information Document Number: MM912F634 Rev. 5.0, 11/2010 Integrated S12 Based Relay Driver with LIN The MM912F634 i.
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