MB91F155
Key Features
- CPU * * * * * * *
- 32-bit RISC (FR30) , load/store architecture, 5-stage pipeline General-purpose registers: 32 bits ×16 16-bit fixed-length instructions (basic instructions) , 1 instruction/ 1 cycle Memory-to-memory transfer, bit processing, barrel shift processing : Optimized for embedded applications Function entrance/exit instructions, and multiple load/store instructions of register contents, instruction systems supporting high level languages Register interlock functions, efficient assembly language description Branch instructions with delay slots : Reduced overhead time in branching executions Internal multiplier/supported at instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles Interrupt (PC and PS saving) : 6 cycles, 16 priority levels (Continued)
- s PACKAGE 144-pin plastic LQFP (FPT-144P-M08) DataSheet 4 U .com
